Chinese Chipmakers Bypass EUV Limits Through Costly Workarounds

Chinese semiconductor manufacturers face a persistent tension between the desire for cutting-edge technology and the restriction of access to the most advanced manufacturing tools. Export controls have effectively locked ASML’s extreme ultraviolet lithography machines outside the country. This barrier forces domestic producers to rely on older deep ultraviolet equipment to fabricate modern processors. While this alternative path allows for the production of capable silicon, it introduces significant financial and technical friction that complicates the long-term competitiveness of the industry.

The core of the issue lies in the specific capabilities of these machines. EUV technology uses 13.5nm-wavelength light to print the finest features on modern chips. ASML is the sole producer of these systems, creating a critical bottleneck. Some analysts estimate that the gap in lithography capability between China and Western nations is currently at least five years. This disparity defines the current state of the global chip supply chain and influences how domestic firms approach their manufacturing strategies.

Despite these constraints, Chinese firms have demonstrated surprising progress. A 2023 examination of Huawei’s Mate 60 Pro revealed that its Kirin 9000S processor was manufactured by SMIC using a second-generation 7nm-class process that did not require EUV. More recent analysis of the Kirin 9030 suggests that SMIC has moved its DUV-based process closer to the density levels associated with 5nm manufacturing. While this remains behind the leading processes from TSMC and Samsung, it represents a notable achievement in working around hardware limitations.

The technical method enabling this progress is known as multiple patterning. Instead of printing a complex layer in a single pass, manufacturers break the design into several simpler patterns and build the layer incrementally. Chris Mack, co-founder and CTO of Fractilia, notes that the industry has long understood the economic trade-offs involved. He explains that three exposures on a 193 immersion tool historically cost about the same as one EUV exposure. However, once the process requires four masks, EUV becomes the more economical option.

Beyond cost, quality control presents a major challenge. Each new pattern must align precisely with previously etched layers. More exposures lead to accumulated overlay errors and process variation. Designers can mitigate this by adding space around features, but this increases the overall chip size. A larger chip reduces the number of dies per wafer, a significant loss when considering that wafers cost tens of thousands of dollars. As Mack puts it, "You don't sell wafers, you sell die," highlighting the economic importance of maximizing usable space on each wafer.

Data from the memory sector provides further evidence of this efficiency gap. A June report from Morgan Stanley estimated that CXMT, a Chinese DRAM maker, produces only about one-third as many bits per wafer as its Western competitors. The firm described lithography access as a "hard ceiling" for Chinese memory development. Mack also emphasized that process node labels like 5nm or 3nm have limited meaning in isolation. He noted that while SMIC’s N+3 process is a step forward, it remains significantly less scaled than established 5nm processes from Samsung and TSMC.

However, DUV technology still has room for advancement. Micron successfully developed its 1-alpha DRAM without EUV by utilizing multiple patterning and tight process control. Mack observed that Micron "pushed 193 farther than any of the other memory makers did." Morgan Stanley considers CXMT’s planned move to 1-alpha DRAM, intended for HBM3e, achievable without EUV. Additionally, researcher Douglas Fuller from Copenhagen Business School expects that advanced packaging will allow firms to use DUV for the latest DRAM generations by the end of the decade.

Even so, the economic limits of DUV are becoming apparent. Micron eventually turned to EUV for its 1-gamma DRAM, which offers more than 30% greater bit density than the previous generation. While EUV has its own drawbacks, such as stochastic effects that require higher exposure doses, Mack stated he would be "hard pressed" to believe a 3nm or 2nm node could be economically viable without it. This suggests that while DUV is a viable stopgap, it may not support the most advanced logic chips indefinitely.

Chinese chipmakers are unlikely to stall, but they will continue to accept larger dies, poorer yields, or longer manufacturing times. They can also expand capacity to offset efficiency losses. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV while increasing its share of global DRAM bit supply from 14% in 2026 to 16% in 2028. The bank also predicts China’s AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, even as persistent gaps remain in EUV, HBM, and advanced software.

This strategy allows Chinese manufacturers to maintain momentum in a constrained environment. By leveraging existing DUV capabilities and focusing on capacity expansion, they can continue to meet growing demand. The long-term sustainability of this approach depends on how well these firms can manage the accumulating costs and technical limitations. As the industry moves forward, the balance between cost, yield, and capability will remain a central factor in determining the global competitive landscape.