Memory Markets: Micron Targets 42 Gb/mm2 Density in Late 2027

Micron Technology expects to begin high-volume production of its G11 3D NAND flash in the second half of 2027. The company detailed the roadmap at an industry event this week, positioning the new memory to serve data centers, client solid-state drives, and emerging artificial intelligence applications.

The G11 generation is designed to double the storage density of Micron’s current G9 product. While G9 technology offers approximately 21 gigabits per square millimeter in triple-level-cell form, G11 will reach about 42 gigabits per square millimeter. This density increase exceeds the next-generation offerings from competitors Kioxia and Samsung, which are currently developing their BiCS10 and V10 architectures.

Performance metrics for the new chips show substantial gains in speed and efficiency. Input/output speeds will rise from 3,600 megatransfers per second to 5,400 megatransfers per second, a 50 percent increase. Simultaneously, the energy required to transfer each bit of data will drop by more than 25 percent. These improvements aim to meet the higher bandwidth and lower power consumption demands of AI workloads.

A key architectural shift in G11 is the adoption of wafer-on-wafer bonding. This process allows Micron to fabricate the memory array and the peripheral circuitry on separate wafers, optimizing each for its specific function before joining them. Although the company has employed CMOS-under-array designs for several generations, bonding provides greater flexibility in optimizing logic and memory components independently.

Scott DeBoer, Micron’s president and chief technology and products officer, confirmed the use of the bonding technology. DeBoer stated that the company had previously pledged to introduce the method when it became cost-effective and relevant to product specifications. He described G11 as the world's most advanced NAND and declared that the current market timing is appropriate for the technology.

Micron has not disclosed the exact number of active wordline layers in the G11 design, noting only that the chip will surpass 400 layers. The company attributes the density increase to a combination of additional layers and a smaller memory cell pitch. More technical details regarding the specific layer count are expected to be released in 2027, closer to the start of volume production.